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agnd and pgnd must be connected together externally description the a3979 is a complete microstepping motor driver with built-in translator, designed as a pin-compatible replacement for the successful a3977, with enhanced microstepping ( 1 / 16 step) precision. it is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes, with an output drive capacity of up to 35 v and 2.5 a. the a3979 includes a fixed off-time current regulator that has the ability to operate in slow, fast, or mixed decay modes. this current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. the translator is the key to the easy implementation of the a3979. it allows the simple input of one pulse on the step pin to drive the motor one microstep, which can be either a full step, half, quarter, or sixteenth, depending on the setting of the ms1 and ms2 logic inputs. there are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. the a3979 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. internal synchronous-rectification control circuitry is provided to improve power dissipation during pwm operation. internal circuit protection includes: thermal shutdown with hysteresis, uvlo (undervoltage lockout), and crossover-current protection. special power-on sequencing is not required. the a3979 is supplied in a low-profile (height 1.20 mm), 28-pin tssop with exposed thermal pad. the package is lead (pb) free, with 100% matte tin leadframe plating. 26184.23f features and benefits ? 2.5 a, 35 v output rating ? low r ds(on) outputs: 0.28 source, 0.22 sink, typical ? automatic current decay mode detection/selection ? 3.0 to 5.5 v logic supply voltage range ? slow, fast or mixed current decay modes ? home output ? synchronous rectification for low power dissipation ? internal uvlo and thermal shutdown circuitry ? crossover-current protection microstepping dmos driver with translator package: 28 lead tssop (suffix lp) with exposed thermal pad pin-out diagram a3979 7 8 9 10 11 12 13 6 5 20 19 18 17 16 15 21 22 14 1 2 3 4 26 25 28 27 24 23 vcp pgnd vreg step out2b reset sr vbb2 pfd rc1 agnd ref rc2 vdd out2a ms2 ms1 sense2 sense1 home dir out1a enable out1b cp2 cp1 sleep vbb1 translator and control logic 8 reg charge pump pwm timer not to scale
dmos microstepping driver with translator a3979 2 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com selection guide part number packing A3979SLPTR-t 4000 pieces per reel absolute maximum ratings load supply voltage v bb 35 v output current i out output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. 2.5 a logic supply voltage v dd 7.0 v logic input voltage range v in t w > 30 ns ?0.3 to v dd + 0.3 v t w < 30 ns ?1 to v dd + 1 v sense voltage v sense 0.5 v reference voltage v ref v dd v operating ambient temperature t a range s ?20 to 85 c junction temperature t j (max) 150 c storage temperature t stg ?55 to 150 c
dmos microstepping driver with translator a3979 3 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional block diagram sense1 sense2 vreg vcp cp1 dac vdd pwm timer: pwm latch blanking mixed decay dac step dir ms1 pwm timer: pwm latch blanking mixed decay cp2 charge pump vbb1 out1a out1b vbb2 out2a out2b translator gate drive dmos full bridge dmos full bridge 0.22 f ms2 ref r s2 c s2 r s1 c s1 0.22 f uvlo and fault logic supply reference supply 4 4 reset sleep enable sr pfd rc2 rc1 home 2 v 0.22 f control logic >47 f load supply r t2 c t2 r t1 c t1 v pfd 0.1 f regulator bandgap exposed thermal pad agnd pgnd (required)
dmos microstepping driver with translator a3979 4 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics at t a = 25c, v bb = 35 v, v dd = 3.0 to 5.5 v (unless otherwise noted) characteristics symbol test conditions min. typ. 1 max. units output drivers load supply voltage range v bb operating 8 ? 35 v during sleep mode 0 ? 35 v output leakage current 2 i dss v out = v bb ? <1.0 20 a v out = 0 v ? <1.0 ?20 a output on resistance r ds(on) source driver, i out = ?2.5 a ? 0.28 0.335 sink driver, i out = 2.5 a ? 0.22 0.265 body diode forward voltage v f source diode, i f = ?2.5 a ? ? 1.4 v sink diode, i f = 2.5 a ? ? 1.4 v motor supply current i bb f pwm < 50 khz ? ? 8.0 ma operating, outputs disabled ? ? 6.0 ma sleep mode ? ? 20 a control logic logic supply voltage range v dd operating 3.0 5.0 5.5 v logic supply current i dd f pwm < 50 khz ? ? 12 ma outputs off ? ? 10 ma sleep mode ? ? 20 a logic input voltage v in(1) 0.7 v dd ??v v in(0) ?? 0.3 v dd v logic input current 2 i in(1) v in = 0.7 v dd ?20 <1.0 20 a i in(0) v in = 0.3 v dd ?20 <1.0 20 a reference input voltage range v ref operating 0 ? v dd v reference input current i ref ?03 a home output voltage v home(1) i home(1) = ?200 a 0.7 v dd ??v v home(0) i home(0) = 200 a?? 0.3 v dd v mixed decay mode trip point v pfdh ? 0.6 v dd ?v v pfdl ? 0.21 v dd ?v gain (g m ) error 3 e g v ref = 2 v, phase current = 38.27% ? ? 10 % v ref = 2 v, phase current = 70.71% ? ? 5.0 % v ref = 2 v, phase current = 100.00% ? ? 5.0 % step pulse width t w 1?? s blank time t blank r t = 56 k , c t = 680 pf 700 950 1200 ns fixed off-time t off r t = 56 k , c t = 680 pf 30 38 46 s crossover dead time t dt synchronous rectification enabled 100 475 800 ns continued on the next page...
dmos microstepping driver with translator a3979 5 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 1 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. 2 negative current is defined as coming out of (sourcing from) the specified device pin. 3 e g = ( [ v ref / 8] ? v sense ) / ( v ref / 8 ). electrical characteristics, continued at t a = 25c, v bb = 35 v, v dd = 3.0 to 5.5 v (unless otherwise noted) thermal shutdown temperature t jsd ? 165 ? c thermal shutdown hysteresis t jsdhys ?15?c uvlo enable threshold v uvlo increasing v dd 2.45 2.7 2.95 v uvlo hysteresis v uvlohys 0.05 0.10 ? v characteristics symbol test conditions min. typ. 1 max. units characteristic symbol test conditions* value units package thermal resistance r ja two-layer pcb with 3.8 in. 2 of copper area on each side connected with thermal vias and to device exposed pad 32 oc/w high-k pcb (multilayer with significant copper areas, based on jedec standard) 28 oc/w *additional thermal information available on allegro web site. thermal characteristics may require derating at maximum conditions, see application information temperature (c) power dissipation, p d (w) 0.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.0 1.5 20 40 60 80 100 120 140 160 maximum power dissipation, p d(max) (r ja = 32 oc/w) (r ja = 28 oc/w) high-k pcb 2-layer pcb with 3.8 in 2 copper per side
dmos microstepping driver with translator a3979 6 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 1. logic interface timing diagram table 1. microstep resolution truth table ms1 ms2 microstep resolution excitation mode l l full step 2 phase h l half step 1-2 phase l h quarter step w1-2 phase h h sixteenth step 4w1-2 phase timing requirements (t a = +25 c, v dd = 5 v, logic levels are v dd and ground) a b c d 50% step ms1/ms2/ dir/reset dwg. wp-042 sleep e a. minimum command active time before step pulse (data set-up time) ..... 200 ns b. minimum command active time after step pulse (data hold time) ............ 200 ns c. minimum step pulse width ...................... 1.0 s d. minimum step low time ......................... 1.0 s e. maximum wake-up time ......................... 1.0 ms
dmos microstepping driver with translator a3979 7 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional description device operation. the a3979 is a complete micro- stepping motor driver with a built-in translator for easy operation with minimal control lines. it is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes. the currents in each of the two output full-bridges (all of the n-channel mosfets) are regulated with fixed off-time pmw (pulse width modulated) control circuitry. at each step, the current for each full-bridge is set by the value of its external current-sense resistor (r s1 or r s2 ), a reference voltage (v ref ), and the output voltage of its dac (which in turn is controlled by the output of the translator). at power-on or reset, the translator sets the dacs and the phase current polarity to the initial home state (shown in figures 2 through 5), and the current regulator to mixed decay mode for both phases. when a step command signal occurs on the step input, the translator automatically sequences the dacs to the next level and current polarity. (see table 2 for the current-level sequence.) the microstep resolution is set by the combined effect of inputs ms1 and ms2 , as shown in table 1. while stepping is occurring, if the next output level of the dacs is lower than the immediately preceeding output level, then the decay mode (fast, slow, or mixed) for the active full bridge is set by the pfd input. if the next dac output level is higher than or equal to the preceeding level, then the decay mode for that full bridge will be slow decay. this automatic current-decay selection improves microstep- ping performance by reducing the distortion of the current waveform due to back emf of the motor. reset input ( r e s e t ). the r e s e t input (active low) sets the translator to a predefined home state (shown in figures 2 through 5), and turns off all of the dmos out- puts. the home output goes low and all step inputs are ignored until the r e s e t input is set to high. home output (home) . the home output is a logic output indicator of the initial state of the translator. at power-on, the translator is reset to the home state (shown in figures 2 through 5). step input (step) . a low-to-high transition on the step input sequences the translator and advances the motor one increment. the translator controls the input to the dacs and the direction of current flow in each winding. the size of the increment is determined by the combined state of inputs ms1 and ms2 (see table 1). microstep select (ms1 and ms2). the input on terminals ms1 and ms2 s elects the microstepping format, as shown in table 1. any changes made to these inputs do not take effect until the next rising edge of a step command signal on the step input. direction input (dir). the state of the dir input deter- mines the direction of rotation of the motor. any changes made to this input does not take effect until the next rising edge of a step command signal on the step input. internal pwm current control. each full bridge is controlled by a fixed?off-time pwm current-control circuit that limits the load current to a desired value, i trip . initially, a diagonal pair of source and sink mos outputs are enabled and current flows through the motor winding and the current sense resistor, r s x . when the voltage across r s x equals the dac output voltage, the current-sense comparator resets the pwm latch. the latch then turns off either the source mos- fets (when in slow decay mode) or the sink and source mosfets (when in fast or mixed decay mode). the maximum value of current limiting is set by the selec- tion of r s and the voltage at the v ref input with a transcon- ductance function approximated by: i trip max = v ref /8r s the dac output reduces the v ref output to the cur- rent-sense comparator in precise steps (see table 2 for % i trip max at each step). i trip = (% i trip max/100) i trip max it is critical that the maximum rating (0.5 v) on either the sense1 and sense2 pins is not exceeded. for full step- ping, v ref can be applied up to the maximum rating of v dd because the peak sense value is 0.707 v ref / 8. in all other modes, v ref should not exceed 4 v. functional description
dmos microstepping driver with translator a3979 8 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com fixed off-time. the internal pwm current-control cir- cuitry uses a one-shot timer to control the duration of time that the mosfets remain off. the one shot off-time, t off , is determined by the selection of external resistors, r t x , and capacitors, c t x , connected from each r c x timing terminal to ground. the off-time, over a range of values of c t = 470 pf to 1500 pf and r t = 12 k to 100 k is approximated by: t off = r t c t rc blanking. in addition to the fixed off-time of the pwm control circuit, the ctx component sets the compara- tor blanking time. this function blanks the output of the current-sense comparators when the outputs are switched by the internal current-control circuitry. the comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, or to switching transients related to the capacitance of the load. the blank time t blank can be approximated by: t blank = 1400c t charge pump (cp1 and cp2). the charge pump is used to generate a gate supply greater than that of vbb for driving the source-side dmos gates. a 0.22 f ceramic capacitor should be connected between cp1 and cp2 for pumping purposes. in addition, a 0.22 f ceramic capacitor is required between vcp and vbb, to act as a reservoir for operating the high-side dmos gates. v reg (vreg) . this internally-generated voltage is used to operate the sink-side dmos outputs. the vreg pin must be decoupled with a 0.22 f capacitor to ground. v reg is internally monitored, and in the case of a fault condition, the dmos outputs of the device are disabled. enable input ( e n a b l e ) . this active-low input enables all of the dmos outputs. when set to a logic high, the outputs are disabled. the inputs to the translator (step, dir, ms1, and ms2), all remain active, independent of the e n a b l e input state. shutdown. during normal operation, in the event of a fault, such as overtemperature (excess t j ) or an undervolt- age on vcp, the outputs of the device are disabled until the fault condition is removed. at power up, and in the event of low v dd , the undervoltage lockout (uvlo) circuit disables the drivers and resets the translator to the home state. sleep mode ( s l e e p ). this active-low control input is used to minimize power consumption when the motor is not in use. it disables much of the internal circuitry includ- ing the output dmos fets, current regulator, and charge pump. setting this to a logic high allows normal operation, as well as start-up (at which time the a3979 drives the motor to the home microstep position). when bringing the device out of sleep mode, in order to allow the charge pump (gate drive) to stabilize, provide a delay of 1 ms before issu- ing a step command signal on the step input. percent fast decay input (pfd). when a step input signal commands a lower output current than the previous step, it switches the output current decay to either slow, fast, or mixed decay mode, depending on the voltage level at the pfd input. if the voltage at the pfd input is greater than 0.6 v dd , then slow decay mode is selected. if the voltage on the pfd input is less than 0.21 v dd , then fast decay mode is selected. mixed decay mode is selected when v pfd is between these two levels, as described in the next section. this terminal should be decoupled with a 0.1 f capacitor. mixed decay operation. if the voltage on the pfd input is between 0.6 v dd and 0.21 v dd , the bridge operates in mixed decay mode, as determined by the step sequence (shown in figures 2 through 5). as the trip point is reached, the device goes into fast decay mode until the voltage on the rcx terminal decays to the same level as voltage applied to the pfd terminal. the time that the device oper- ates in fast decay is approximated by: t fd = r t c t ln (0.6v dd /v pfd ) after this fast decay portion, the device switches to slow decay mode for the remainder of the fixed off-time period.
dmos microstepping driver with translator a3979 9 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com synchronous rectification. when a pwm off- cycle is triggered by an internal fixed?off-time cycle, load current recirculates according to the decay mode selected by the control logic. the a3979 synchronous rectification feature turns on the appropriate mosfets during the decay of the current, and effectively shorts out the body diodes with the low r ds(on) driver. this reduces power dissipation significantly and eliminates the need for external schottky diodes for most applications. the synchronous rectification can be set to either active mode or disabled mode: ? active mode . when the sr input is logic low, active mode is enabled and synchronous rectification can occur. this mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. this prevents the motor winding from conduct- ing in the reverse direction. ? disabled mode. when the sr input is logic high, syn- chronous rectification is disabled. this mode is typi- cally used when external diodes are required to transfer power dissipation from the a3979 package to the external diodes. layout. the printed circuit board on which the device is mounted should have a heavy ground plane. for optimum electrical and thermal performance, the a3979 should be soldered directly onto the board. the load supply terminals, vbb x , should be decoupled with an electrolytic capacitor (>47 f is recommended), placed as close to the device as possible. to avoid problems due to capacitive coupling of the high dv / dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. always drive the logic inputs with a low source impedance to increase noise immunity. grounding. the agnd (analog ground) terminal and the pgnd (power ground) terminal must be connected together externally. all ground lines should be connected together and be as short as possible. a star ground system, centered under the device, is an optimum design. the copper ground plane located under the exposed thermal pad is typically used as the star ground. current sensing. to minimize inaccuracies caused by ground-trace ir drops in sensing the output current level, the current-sense resistors, r s x , should have an independent ground return to the star ground of the device. this path should be as short as possible. for low-value sense resistors, the ir drops in the printed cir- cuit board sense resistor traces can be significant and should be taken into account. the use of sockets should be avoided as they can introduce variation in r s x due to their contact resistance. allegro microsystems recommends a value of r s given by r s = 0.5/i trip max thermal protection. this internal circuitry turns off all drivers when the junction temperature reaches 165c, typical. it is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. thermal shutdown has a hysteresis of approximately 15c. applications information
dmos microstepping driver with translator a3979 10 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 0.00 100.00 92.39 70.71 38.27 ?38.27 ?70.71 ?92.39 ?100.00 0.00 100.00 92.39 70.71 38.27 ?38.27 ?70.71 ?92.39 ?100.00 phase 2 i out2a direction = h (%) phase 1 i out1a direction = h (%) home microstep position slow mixed slow slow mixed slow mixed slow mixed mixed slow step input home output home microstep position home microstep position 100.00 70.71 ?70.71 0.00 ?100.00 100.00 70.71 ?70.71 0.00 ?100.00 phase 2 i out2a direction = h (%) phase 1 i out1a direction = h (%) slow mixed slow mixed slow mixed mixed slow mixed slow mixed slow slow step input home output phase 2 i out2a direction = h (%) phase 1 i out1a direction = h (%) step input home microstep position home microstep position 100.00 70.71 ?70.71 0.00 ?100.00 100.00 70.71 ?70.71 0.00 ?100.00 slow slow home output figure 4. decay modes for quarter-step increments figure 3. decay modes for half-step increments figure 2. decay mode for full-step increments
dmos microstepping driver with translator a3979 11 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 5. decay modes for sixteenth-step increments mixed slow mixed slow mixed slow slow slow 100.00 95.69 88.19 83.15 ?83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.8 0.00 ?100.00 ?95.69 ?88.19 ?77.30 ?70.71 ?63.44 ?55.56 ?47.14 ?38.27 ?29.03 ?19.51 ?9.8 100.00 95.69 88.19 83.15 ?83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.8 0.00 ?100.00 ?95.69 ?88.19 ?77.30 ?70.71 ?63.44 ?55.56 ?47.14 ?38.27 ?29.03 ?19.51 ?9.8 phase 2 i out2a direction = h (%) phase 1 i out1a direction = h (%) home microstep position mixed step input home output
dmos microstepping driver with translator a3979 12 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com table 2. step sequencing settings home microstep position at step angle 45o; dir = h; 360 = 4 full steps full step # half step # 1/4 step # 1/16 step # phase 1 current [% i tripmax ] (%) phase 2 current [% i tripmax ] (%) step angle (o) full step # half step # 1/4 step # 1/16 step # phase 1 current [% i tripmax ] (%) phase 2 current [% i tripmax ] (%) step angle (o) 1 1 1 100.00 0.00 0.0 5 9 33 ?100.00 0.00 180.0 2 99.52 9.80 5.6 34 ?99.52 ?9.80 185.6 3 98.08 19.51 11.3 35 ?98.08 ?19.51 191.3 4 95.69 29.03 16.9 36 ?95.69 ?29.03 196.9 2 5 92.39 38.27 22.5 10 37 ?92.39 ?38.27 202.5 6 88.19 47.14 28.1 38 ?88.19 ?47.14 208.1 7 83.15 55.56 33.8 39 ?83.15 ?55.56 213.8 8 77.30 63.44 39.4 40 ?77.30 ?63.44 219.4 1 2 3 9 70.71 70.71 45.0 3 6 11 41 ?70.71 ?70.71 225.0 10 63.44 77.30 50.6 42 ?63.44 ?77.30 230.6 11 55.56 83.15 56.3 43 ?55.56 ?83.15 236.3 12 47.14 88.19 61.9 44 ?47.14 ?88.19 241.9 4 13 38.27 92.39 67.5 12 45 ?38.27 ?92.39 247.5 14 29.03 95.69 73.1 46 ?29.03 ?95.69 253.1 15 19.51 98.08 78.8 47 ?19.51 ?98.08 258.8 16 9.80 99.52 84.4 48 ?9.80 ?99.52 264.4 3 5 17 0.00 100.00 90.0 7 13 49 0.00 ?100.00 270.0 18 ?9.80 99.52 95.6 50 9.80 ?99.52 275.6 19 ?19.51 98.08 101.3 51 19.51 ?98.08 281.3 20 ?29.03 95.69 106.9 52 29.03 ?95.69 286.9 6 21 ?38.27 92.39 112.5 14 53 38.27 ?92.39 292.5 22 ?47.14 88.19 118.1 54 47.14 ?88.19 298.1 23 ?55.56 83.15 123.8 55 55.56 ?83.15 303.8 24 ?63.44 77.30 129.4 56 63.44 ?77.30 309.4 2 4 7 25 ?70.71 70.71 135.0 4 8 15 57 70.71 ?70.71 315.0 26 ?77.30 63.44 140.6 58 77.30 ?63.44 320.6 27 ?83.15 55.56 146.3 59 83.15 ?55.56 326.3 28 ?88.19 47.14 151.9 60 88.19 ?47.14 331.9 8 29 ?92.39 38.27 157.5 16 61 92.39 ?38.27 337.5 30 ?95.69 29.03 163.1 62 95.69 ?29.03 343.1 31 ?98.08 19.51 168.8 63 98.08 ?19.51 348.8 32 ?99.52 9.80 174.4 64 99.52 ?9.80 354.4
dmos microstepping driver with translator a3979 13 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com terminal list table number name description 1 sense1 sense resistor for bridge 1 2 home logic output 3 dir logic input 4 out1a output a for bridge 1 5 pfd mixed decay setting 6 rc1 analog input for fixed off-time for bridge 1 7 agnd analog ground 8 ref current trip reference voltage input 9 rc2 analog input for fixed off-time for bridge 2 10 vdd logic supply 11 out2a output a for bridge 2 12 ms2 logic input 13 ms1 logic input 14 sense2 sense resistor for bridge 2 15 vbb2 load supply for bridge 2 16 sr logic input 17 r e s e t logic input 18 out2b output b for bridge 2 19 step logic input 20 vreg regulator decoupling 21 pgnd power ground 22 vcp reservoir capacitor 23 cp1 charge pump capacitor 1 24 cp2 charge pump capacitor 2 25 1out1b output b for bridge 1 26 e n a b l e logic input 27 s l e e p logic input 28 vbb1 load supply for bridge 1
dmos microstepping driver with translator a3979 14 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com lp package, 28-pin tssop 1.20 max 0.10 max c seating plane c 0.10 28x 6.10 0.65 0.45 1.65 3.00 3.00 5.00 5.00 0.25 0.65 2 1 28 gauge plane seating plane b a 28 2 1 a terminal #1 mark area b for reference only (reference jedec mo-153 aet) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 sop65p640x120-29cm); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) 4.40 0.10 6.40 0.20 (1.00) 9.70 0.10 c c 0.60 0.15 4 4 0.15 +0.05 ?0.06 0.25 +0.05 ?0.06
dmos microstepping driver with translator a3979 15 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com copyright ?2005-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. f june 21, 2013 update decay charts

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